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A method for determining a test-chip sample size to estimate effectively the electrical parameter distributions on an integrated circuit wafer is presented. This method gives relations among sample size and the figure of merit for four statistical techniques (trimmed mean, biweighted mean, median, and arithmetic mean) by which estimates are calculated. To demonstrate its use, the method has been applied to the evaluation of a CMOS fabrication process. Measurements on wafers completely patterned with identical test chips were used to determine actual parameter distributions for an entire wafer (true parameter values). Estimates of true parameters were determined using a site-selection plan which is representative of sampling plans used in industry. The four statistical techniques were used to compute estimates for electrical parameters and their respective figures of merit. These estimates were compared with the true parameter values determined from testing all test chips on the wafer.