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Design methodology of a 1.2-μm double-level-metal CMOS technology

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8 Author(s)

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-μm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.

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Solid-State Circuits, IEEE Journal of  (Volume:19 ,  Issue: 1 )