By Topic

Design and fabrication of depletion GaAs LSI high-speed 32-bit adder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)

A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:18 ,  Issue: 5 )