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Design and fabrication of depletion GaAs LSI high-speed 32-bit adder

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6 Author(s)

A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:18 ,  Issue: 5 )

Date of Publication:

Oct. 1983

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