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A multiplexed 4 Mbit bubble memory device

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2 Author(s)

A 4-Mbit magnetic bubble memory has been designed and demonstrated which is architecturally compatible with an 1-Mbit memory. The design goals for the memory were to achieve user software compatibility and pin-for-pin interchangeability. To achieve this, one key 4-Mbit device feature was additional multiplexing. This was obtained by a novel application of thin-film detectors and replicate generators along with other function designs. The result is a 4 bit/cycle write and read operation and a page length of 512 bits. The margins for the functions are shown to be comparable to those for the 1-Mbit process while the detector signal is over three times larger. The 1-Mbit process is extended to the 4-Mbit device by adding a thin permalloy level which requires one additional critical alignment and scaling geometries to give a 0.75-/spl mu/m minimum feature size on a 5.5-/spl mu/m square memory cell.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:18 ,  Issue: 5 )