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An NMOS DRAM controller for use in microcomputer systems based on the iAPX-86 and iAPX-286 microprocessor families or on the Multibus system bus is described. The controller provides complete support for dual-port memories and memories with error checking and correction. The controller has programmable attributes for configuring it to the particular requirements of the system. The controller uses parallel arbitration to minimize arbitration delay. A memory cycle will start on the same clock edge that samples a command if the cycle has been previously enabled. Novel logic and circuit design techniques have been used to achieve 16 MHz operation, 20 ns input setup time, and 35 ns output delay time.