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A monolithic solution to the problem of sending and receiving data over power lines has been developed. The self-contained bipolar chip handles half-duplex serial data at up to 4K baud by FSK modulating a carrier frequency set at between 50 and 300 kHz. The transmitter section drives the line with a low distortion (0.1 percent) sine wave to minimize potential RFI. The 200 mW output originates from a transient-hardened on-chip transistor, and is in the form of a current that adapts to the widely varying power line impedance. The PLL receiver section has a sensitivity of 1 mV and contains a special impulse noise filter to reduce the effects of power line noise. Data of virtually any coding will pass through the system.