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A versatile function generator chip implemented in an I/sup 2/L gate array

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6 Author(s)

A mask-programmable I/SUP 2/L gate array is used to implement a versatile function generator chip which employs a 9 bit input data set to generate a 9 bit digital ramp. The chip utilizes a novel ripple adder design that uses only eight I/SUP 2/L inverters per full adder and requires only on I/SUP 2/L gate delay for carry propagation per bit. The ramp can wobbulate between an initial and a final frequency or have a constant frequency. The initial and final frequencies, the wobbulation rate, the ramp amplitude and frequency, and the wobbulation mode are all controlled from the input data. The output may also be selected as a rectangular wave with variable duty cycle. Typical input data setup and hold times of about 75 ns each were obtained for this design. A gate utilization factor ~95 percent has been achieved in programming the gate array.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:17 ,  Issue: 4 )