The characteristic features of subthreshold operation of dual-gate MOS transistors are investigated. A simple analytical approach is formulated for the calculation of surface potential in short-channel dual-gate MOSFETs up to the punch through region. The model takes into account the two-dimensional sharing of bulk depletion charge among the source, first gate, second gate, and drain. The threshold voltages are predicted accurately as functions of applied biases and device parameters. Excellent agreement is found between theory and experimental data obtained from measurements an overlapping-gate n-channel devices. The short-channel effects due to either gate-induced or drain-induced barrier lowering are discussed and compared to those normally encountered in single-gate MOS transistors.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:17
,
Issue:
3
)
Date of Publication: Jun 1982