By Topic

Structured Logic Design of Integrated Circuits Using the Storage/Logic Array (SLA)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

The Storage/Logic Array (SLA), a form of structured logic derived from PLA's, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLA's are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLA's) are made. Segmenting SLA's with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLA's in I2L, NMOS, and CMOS are described and compared. I2L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSL. Programming techniques and examples are given.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:17 ,  Issue: 2 )