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In sealed technologies, performance improvements become increasingly tilted by interconnect parasitic. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities/spl rho//sub S/ and /spl rho//sub D/, and the specific contact resistivity /spl rho//sub c/, are incorporated, unlike earlier models for contact holes only in which /spl rho//sub S/ =0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 /spl mu/m, a-factor-of two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.