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The design of fast low-power silicon LSI MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8×8 and 10×10 bit TTL-compatible multipliers, fabricated with a 2.5 μm silicon MESFET technology (1.5-2 μm effective dimensions) is compared to the simulations.