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Reports on the experimental results of a 4-bit charge-coupled A/D converter which was proposed earlier by the authors, and has been implemented in a monolithic chip form. It was fabricated using p-channel CCD technology and has a die size of 4200 mil/SUP 2/. The typical operating frequency range was from 250 Hz to 100 kHz. A discussion is made on a layout technique to conserve the nominal binary ratio of (8:4:2:1) among the areas of four charge-measuring potential wells (M wells). The effect of `dump slot', which has been hypothesized as the cause of excessive nonlinearity (≥1/2 LSB) in the A/D conversion, is described. A novel input scheme called `slot zero insertion', which has been devised to circumvent the `dump slot' effect, is described.