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Interconnection delays in MOSFET VLSI

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1 Author(s)

Although VLSI MOSFET devices have small inherent delays, the RC time constant of the interconnections limits the circuit maximum frequency of operation. A circuit-based solution to this problem, rather than a technology-based solution, is to use circuit configurations that maximize the charging/discharging currents delivered to the interconnections. This paper examines the different MOSFET circuit configurations based on the ability to charge/discharge the RCs of the interconnections and concludes that two circuit configurations are most suitable for VLSI: CMOS and a proposed current steering NMOS. In the latter configuration, the distributed RC network of the interconnection is included in a charging/discharging circuit path which is part of a difference stage. A multisource MOSFET structure is used in the design of the difference stage, in a common-drain/common-gate configuration to maximize the charging/discharging currents. Computer simulation using SPICE 2 and experimental measurements are used to confirm the predicted performance.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:16 ,  Issue: 5 )