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A single-chip CMOS PCM codec with filters

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6 Author(s)

A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:16 ,  Issue: 4 )

Date of Publication:

Aug. 1981

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