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The single device well (SDW) memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells and thus a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 μm technology, an SDW memory cell consumes an area of 600 μm/SUP 2/ and has an average power consumption of 10 μW at 5 V supply. Another version of the cell using a polyresistor is also discussed.