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The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.
Date of Publication: Oct. 1980