By Topic

Threshold-Sensitivity Minimization of Short-Channel MOSFET's by Computer Simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and extensive use of a two-dimensional device simulation. This structure, which can be realized through DSA technology, obtains adequate tolerances for both the channel length and applied drain voltage in the 1-μm channel-length MOSFET; the anticipated channel-length tolerance (Delta L) for maintaining the threshold-voltage fluctuation to within ±10 percent is estimated to be ±0.25 μm when Vd = 5.0 V and gate-oxide thickness tox = 30 nm. With this tolerance, threshold sensitivity to drain voltage drops to one-third in a conventional MOSFET. In a 0.5-μm channel-length MOSFET, Delta L is estimated to be ±0.7 μm when Vd = 3.0 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:15 ,  Issue: 4 )