Skip to Main Content
The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of -2 Omega//spl square/ have been evaluated. The gate metallization typically consisted of 2.5 k/spl Aring/ TaSi/sub 2//2.5 k/spl Aring/ poly-Si, which was sintered prior to patterning with a CF/sub 4//O/sub 2/ plasma etch. Measurements were made to determine the metal work function, oxide freed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-/spl Aring/ SiO/sub 2/, As-implanted source/drain), V/sub T/ and Beta measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n+ poly-Si gates. Static and dynamic bias-temperature aging stability of the V/sub FB/ is excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.