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Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CC1/sub 3/F gas. The Si to SiO/sub 2/ etch-rate ratio was 5:1. This etch process in CC1/sub 3/F was interpreted as mainly involving physical reaction as opposed to etching in SF/sub 6/. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wet-etch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si/sub 3/N/sub 4/, polysilicon, SiO/sub 2/, and aluminum, was applied to, the fabrication of a 1-kbit static RAM with 1-/spl mu/m minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-/spl mu/m MOSLSI manufacturing process.