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A 64 Kbit dynamic RAM is described. The RAM features a novel memory cell using a polysilicon-dielectric-polysilicon (PDP) capacitor. This structure provides performance and density advantages over the conventional approaches. A new sense amplifier configuration is also described in detail. It multiplexes two pairs of bit lines for each sense amplifier. Thus the number of memory cells per bit line is halved. This reduces the length of each bit line, thereby increasing the signal voltage available to the sense amplifier. A compatible dummy cell design is included in the discussion. Using conservative processing (3.5 /spl mu/m device channel length with 700 /spl Aring/ gate oxide thickness) a die size of 3.2 mm/spl times/7.9 mm is achieved. Experimental data are presented in the text.