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An electrically alterable nonvolatile memory cell using a floating-gate structure

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4 Author(s)

An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 /spl mu/m/SUP 2/, and using an advanced n-channel, polysilicon gate process. Cell programming occurs via hot-electron injection, exhibiting three distinct operating regimes. Erase, on the other hand, is based on field emission from floating gate to control gate. The magnitude of electrical erase is determined by applied bias, device parameters, and processing history, particularly the interlevel oxidation temperature. Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design. A 5-V, 16K high-speed EAROM has been developed which shows successful programming and erase behaviour at nominal voltages of 25 and 35 V, respectively.

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Solid-State Circuits, IEEE Journal of  (Volume:14 ,  Issue: 2 )