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A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an ECL gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 /spl mu/m/SUP 2/ gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000 /spl mu/m/SUP 2/ gate area has been successfully developed.
Date of Publication: April 1979