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Describes the design of an analog attenuator integrated circuit having loss settings that can be determined by remote digital control. The circuit uses a weighted MOS capacitor array to effect losses of 0-16.5 dB in steps of 0.1 dB. Each loss setting is accurate to /spl plusmn/0.02 dB. Two approaches to the circuit realization are described: a CMOS version that includes a digital memory to permit retention of loss settings for a few hours, thereby bridging brief power failures, and a more compact NMOS version that contains all the analog components on a single chip.