Referenced Items are not available for this document.
A small 16K dynamic RAM utilizing a new memory cell configuration is described. The new cell has two selector transistors and makes a very short bit line possible. The memory on 8 mm/SUP 2/ is built in a scaled double polysilicon technology with 3.5 /spl mu/m line width. First samples achieved an access time of 160 ns.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:13
,
Issue:
5
)
Date of Publication: Oct. 1978
- Page(s):
- 708 - 711
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1978.1051124
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Oct. 1978
- Sponsored by :
- IEEE Solid-State Circuits Society
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