By Topic

A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/sup 2/

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:13 ,  Issue: 3 )