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A Monte Carlo analysis is presented for the design of input gates in MOS LSI custom static random logic circuits implemented in NORs, NANDs, AOIs, OAIs, etc. The design approach is algorithmic and suited for CAD applications in multi-part-number logic chip design. The algorithms are derived and their usage illustrated for Weinberger chip layouts using circuit-level approximations, assumptions, and criteria.
Date of Publication: Oct. 1977