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A new circuit configuration for a single-transistor cell using Al-gate technology with reduced dimensions

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A single-transistor memory cell in Al-gate technology with 2.5 /spl mu/m line width with a new circuit configuration is introduced. In this cell, the ground line of one cell and the word line of the cell opposite the bit line share the same line. This circuit configuration leads to memory cells having a bit density of 5720 bit/mm/SUP 2/ even though it uses a single layer metallization. The voltage conditions in this cell differ from those in conventional storage cells, but do not reduce the operation range of the new cell. As design and circuit studies have shown, a 32 kbit memory can be realized on a chip area of about 15.4 mm/SUP 2/, having an access time of 200 ns and a power dissipation of 500 mW.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:12 ,  Issue: 3 )

Date of Publication:

June 1977

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