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A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.