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Process technology for radiation-hardened CMOS integrated circuits

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3 Author(s)

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:11 ,  Issue: 4 )