Referenced Items are not available for this document.
A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:11
,
Issue:
4
)
Date of Publication: Aug 1976
- Page(s):
- 459 - 465
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1976.1050759
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Aug 1976
- Sponsored by :
- IEEE Solid-State Circuits Society
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