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On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

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1 Author(s)

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 μm×240 μm. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 μA. The output impedance is 3.2 MΩ.

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Solid-State Circuits, IEEE Journal of  (Volume:11 ,  Issue: 3 )