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A static 2048-bit read/wire memory chip for main stores is described. It uses a modified 6-device memory cell in an n-channel MOSFET technology. To exploit the potential of the given MOSFET technology with respect to the cost/performance ratio and the power-delay product, special provisions are taken. The power is kept low by the gate driver concept as well as by clocked peripheral circuits. High performance is achieved with fast peripheral circuits, the delayed chip select concept, and a bipolar sense amplifier which also supplies the bit-line restore voltage. Circuits are presented which successfully utilize the on-chip tracking to reduce the impact of device parameter tolerances on worst case power and performance. It is shown how the memory chip is packaged on modules, cards, and boards to build up functional memory units.
Date of Publication: June 1976