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Describes a monolithic circuit consisting of an array of 8 voltage comparators, a resistive voltage divider, and associated logic circuits. Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage. A Gray-code output minimizes the problem of comparator indecision. The principal error sources are an asymmetry-induced comparator offset with 2-mV standard deviation and a thermally induced offset of a much as /spl plusmn/2.5 mV, dependent on signal history. The quantizer has been incorporated in an experimental 6-bit 200 megasample/s (MS/s) A/D converter.