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Emitter function logic-logic family for LSI

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1 Author(s)

A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:8 ,  Issue: 5 )

Date of Publication:

Oct. 1973

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