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Five-transistor memory cells in ESFI MOS technology

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2 Author(s)

Compared with a conventional six-transistor memory cell in complementary MOS technology, a five-transistor cell only needs about 70 percent of the area. Memory matrices have been manufactured on epitaxial silicon films on insulators, using such cells with an area of 5700 μm/SUP 2/ (9 mil/SUP 2/). In addition, proposals for a sense circuit are made and the typical data of a 2048-b memory chip are estimated.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:8 ,  Issue: 5 )