Cart (Loading....) | Create Account
Close category search window

A 4096-B one-transistor per bit random-access memory with internal timing and low dissipation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

Some details of a 4096-b p-channel random-access memory with a one-transistor per bit cell are discussed. The main features of the design are the sensitive sense-refresh amplifier, allowing a storage capacitance of only 0.065 pF, application of the bootstrap principle to obtain an access time of 400 ns, a power dissipation of 150 mW, and the implementation of a new, fast shift register as an internal timing circuit. This timing circuit generates the memory clock signals, reducing the number of external clock signals to one clock and a chip select signal. The chip size is 3.01/spl times/4.44 mm/SUP 2/.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:8 ,  Issue: 5 )

Date of Publication:

Oct. 1973

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.