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Some details of a 4096-b p-channel random-access memory with a one-transistor per bit cell are discussed. The main features of the design are the sensitive sense-refresh amplifier, allowing a storage capacitance of only 0.065 pF, application of the bootstrap principle to obtain an access time of 400 ns, a power dissipation of 150 mW, and the implementation of a new, fast shift register as an internal timing circuit. This timing circuit generates the memory clock signals, reducing the number of external clock signals to one clock and a chip select signal. The chip size is 3.01/spl times/4.44 mm/SUP 2/.