Cart (Loading....) | Create Account
Close category search window
 

A dynamic delay line with a bipolar one-transistor cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

A new bipolar one-transistor cell for the storage of analog information is described. This cell forms the basis of a 256-sample dynamic delay line, where 16/spl times/16 cells of a two-dimensional array are successively accessed. The circuitry for the generation of the selection voltages is specially designed in order to make the power dissipation independent of the size of the delay line.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:8 ,  Issue: 4 )

Date of Publication:

Aug. 1973

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.