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The nonlinear properties of digital signal transfer through charge-coupled device and bucket-brigade shift registers are considered in terms of adjacent bit charge levels. A signal transfer efficiency is defined and shown to be a useful parameter for charge-transfer device shift register simulation. Approximate equations are developed for the worst case output bit levels and an approximate formula for the optimum input `fat' zero level, with respect to the worst case output signal `window', is obtained. The analysis includes only the intrinsic incomplete charge transfer properties of CTD's under square-wave clock pulsing conditions. Comparison of the theory and preliminary experimental results for CCD indicate good quantitative agreement.