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High-performance low-power CMOS memories using silicon-on-sapphire technology

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2 Author(s)

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-μm channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 μW/bit (quiescent) and 10 μW/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 μW/bit.

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Solid-State Circuits, IEEE Journal of  (Volume:7 ,  Issue: 2 )