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Integrated MOS analog delay line

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3 Author(s)

A 16-stage, fixed or variable analog delay line that makes use of integrated p-channel MOS field-effect transistors is described. The delay line relies on `sample' and `hold' techniques and makes use of the inherent characteristics of p-channel MOS transistors. The delay line provides unit gain with a dynamic range of 1 volt. The bandwidth of the delay line is 0.8 MHz under nonsampling conditions. The lowest sampling rate was found to be 50 Hz. A built-in capacitive compensation technique using signals opposite in phase reduces feedthrough of the sampling signal and final filtering requirements. Investigation of the problems of obtaining unity gain and dynamic range led to the development of a computer-aided analysis that provides a family of dc transfer characteristics of cascaded p- channel MOS `half-stages' when a variation of either a material or electrical parameter is made.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:4 ,  Issue: 4 )