Cart (Loading....) | Create Account
Close category search window

A monolithic junction FET-n-p-n operational amplifier

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

A monolithic operational amplifier with junction FET inputs in combination with n-p-n bipolar transistors is described. Both dc and small signal analysis of the amplifier are carried out. Electrically the devices are comparable with discrete state-of-the- art p-channel FET's. The circuits are fabricated with a process requiring a single diffusion more than standard techniques. The process is reproducible enough to allow economical fabrication. The amplifier realizes input currents of less than 1 nA, a minimum slewing rate at unity gain of 75 V//spl mu/s and bandwidths in excess of that of any monolithic operational amplifier reported to date.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:3 ,  Issue: 4 )

Date of Publication:

Dec. 1968

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.