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Memory-efficient turbo decoder architectures for LDPC codes

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2 Author(s)
M. M. Mansour ; iCIMS Res. Center, Illinois Univ., Urbana, IL, USA ; N. R. Shanbhag

In this paper, we propose a turbo decoding message-passing (TDMP) algorithm to decode regular and irregular low-density parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase message-passing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations). Second, the corresponding decoder architecture has a significantly reduced memory requirement that amounts to a savings of (75 + 25n/Σ node-degrees)% > 75% for code-length n. A decoder architecture featuring the TDNW algorithm is also presented. Furthermore, we propose a new structure on the parity-check matrix of an LDPC code based on permutation matrices aimed at reducing interconnect complexity and improving decoding throughput. In addition, we construct a wide range of LDPC codes based on Ramanujan graphs which possess this structure.

Published in:

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

Date of Conference:

16-18 Oct. 2002