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A 54 Mbps (3,6)-regular FPGA LDPC decoder

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2 Author(s)
Tong Zhang ; Dept. of Electr. & Comput. Eng., Minnesota Univ., USA ; Parhi, K.K.

Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over an AWGN channel.

Published in:

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

Date of Conference:

16-18 Oct. 2002

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