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Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implementing conventional block-floating-point arithmetics. This paper describes an actual implementation of the DSP architecture on a field programmable gate array (FPGA) platform. Some signal processing quality evaluation results are also presented for two audio applications that are realized on the DSP architecture.