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Finite field multiplier using redundant representation

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4 Author(s)
Huapeng Wu ; Dept. of Electr. & Comput. Eng., Windsor Univ., Ont., Canada ; Hasan, M.A. ; Blake, I.F. ; Shuhong Gao

This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclotomic ring which is based on the elegant multiplicative structure of a cyclic group. One important feature of our architectures is that they provide area-time trade-offs which enable us to implement the multipliers in a partial-parallel/hybrid fashion. This hybrid architecture has great significance in its VLSI implementation in very large fields. The squaring operation using the redundant representation is simply a permutation of the coordinates. It is shown that, when there is an optimal normal basis, the proposed bit-serial and hybrid multiplier architectures have very low space complexity. Constant multiplication is also considered and is shown to have an advantage in using the redundant representation.

Published in:

Computers, IEEE Transactions on  (Volume:51 ,  Issue: 11 )