Referenced Items are not available for this document.
Although the full radix-4 CORDIC algorithm is efficient compared to the standard radix-2 version, the scale-factor overhead causes its improvement to be limited. In this work, an algorithm and its associated architecture have been proposed for parallel compensation of the scale factor for the radix-4 CORDIC algorithm in the rotation mode. The proposed method, which makes no prior assumptions about the elementary angles of rotation, reduces the latency from n to (n/2)+3, where n is the precision length in bits, at the cost of a reasonable increase in hardware complexity. The architecture presented relates to the redundant signed-digit number system. The architecture has been modelled in VHDL and simulated to establish its functional validity.
Published in:
Computers and Digital Techniques, IEE Proceedings -
(Volume:149
,
Issue:
5
)
Date of Publication: Sep 2002
- Page(s):
- 219 - 228
- ISSN :
- 1350-2387
- INSPEC Accession Number:
- 7469045
- Digital Object Identifier :
- 10.1049/ip-cdt:20020427
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 10 December 2002
- Issue Date :
- Sep 2002
- Sponsored by :
- IET
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