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High-performance compensation technique for the radix-4 CORDIC algorithm

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2 Author(s)
Rao, P.R. ; Dept. of Electron. & Commun. Eng., Indian Inst. of Technol., Guwahati, India ; Chakrabarti, I.

Although the full radix-4 CORDIC algorithm is efficient compared to the standard radix-2 version, the scale-factor overhead causes its improvement to be limited. In this work, an algorithm and its associated architecture have been proposed for parallel compensation of the scale factor for the radix-4 CORDIC algorithm in the rotation mode. The proposed method, which makes no prior assumptions about the elementary angles of rotation, reduces the latency from n to (n/2)+3, where n is the precision length in bits, at the cost of a reasonable increase in hardware complexity. The architecture presented relates to the redundant signed-digit number system. The architecture has been modelled in VHDL and simulated to establish its functional validity.

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Computers and Digital Techniques, IEE Proceedings -  (Volume:149 ,  Issue: 5 )