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Steady-state error minimisation technique for single-phase PWM inverters

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1 Author(s)
Se-Kyo Chung ; Dept. of Control & Instrum. Eng., Gyeongsang Nat. Univ., Kyungnam, South Korea

A steady-state error minimisation technique of a single-phase pulsewidth modulated (PWM) inverter is presented. This technique employs a phase-locked loop concept utilising the phase difference between the capacitor voltage and current, which is similar to the dq transform of three phase variables. The experimental results are provided to show the effectiveness of this approach.

Published in:

Electronics Letters  (Volume:38 ,  Issue: 22 )

Date of Publication:

24 Oct 2002

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