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1 V CMOS output stage with excellent linearity

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3 Author(s)
Aloisi, W. ; Dipt. Elettrico, Elettronico e Sistemistico, Catania Univ., Italy ; Giustolisi, G. ; Palumbo, G.

A CMOS low-voltage output stage based on a push-pull topology is proposed. It is driven by a differential signal and its symmetric topology provides excellent intrinsic linearity. It can work with a power supply as low as 1 V and when loaded with a 500 Ω resistor it exhibits negligible even harmonic components whilst odd components are maintained well below -20 dB up to 900 mVpp of the output signal. Moreover, the output stage includes a simple current control which accurately sets the bias condition.

Published in:

Electronics Letters  (Volume:38 ,  Issue: 22 )