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The planar rectilinear Steiner tree problem has been extensively studied. The common formulation ignores circuit fabrication issues such as multiple routing layers, preferred routing directions, and vias between layers. In this paper, the authors extend a previously presented planar rectilinear Steiner tree heuristic to consider layer assignment, preferred routing direction restrictions, and via minimization. They use layer-specific routing costs, via costs, and have a minimum cost objective. Their approach combines the low computational complexity of modern geometry-based methods with much of the freedom enjoyed by graph-based methods. When routing costs mirror those of traditional planar rectilinear Steiner problems, the authors' approach obtains close to 11% reductions in tree lengths, compared to minimum spanning trees; this is on par with the performance of the best available Steiner heuristics. When via costs are significant and layer costs differ, they observe average cost reductions of as much as 37%. Their method can also reduce the number of vias significantly.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:21 , Issue: 11 )
Date of Publication: Nov 2002