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This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite-state machine synthesis. The approach achieves fast single-output logic minimization that yields solutions that are exact in the number of literals. This paper presents algorithms and hazard constraints targeting both generalized C-element and two-level standard gate implementations. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms. The algorithm achieves fast logic minimization by using compacted state graphs, cover tables, and a divide-and-merge algorithm for efficient single output minimization. The exact two-level hazard-free logic minimizer presented in this paper finds a minimal number of literal solutions and is several orders of magnitude faster than existing literal exact methods for the largest benchmarks available to date. This includes a benchmark that has never been possible to solve exactly in number of literals before.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:21 , Issue: 11 )
Date of Publication: Nov 2002